1. Field of the Invention
The present invention relates to a laminated electronic component including a plurality of terminal electrodes.
2. Description of the Related Art
In an electric supply source of a central processing unit (CPU) mounted in a digital electronic device, a reduction in voltage advances while a load current is increased. Therefore, suppressing a fluctuation in power supply voltage within an allowable value range with respect to a sudden change in load current becomes very difficult, and hence a multilayer capacitor called a decoupling capacitor is connected with a power supply. Further, at the time of a transitional fluctuation in load current, a current is supplied from this multilayer capacitor to a CPU, thereby suppressing a fluctuation in power supply voltage.
In recent years, with a further increase in an operating frequency of a CPU, a load current and its speed are increased. Therefore, in the multilayer capacitor used as the decoupling capacitor, there is a demand for an increase in equivalent series resistance (ESR).
In a multiterminal type multilayer capacitor disclosed in Patent Reference 1, an extraction electrode for connection with a terminal electrode is provided to an internal electrode in each layer of a ceramic element assembly, and such an extraction element is led onto a side surface of the ceramic element assembly. The terminal electrode is formed on the side surface of the ceramic element assembly by plating or the like and joined to the extraction electrode.
In order to obtain a high ESR in this type of multilayer capacitor, the number of layers must be reduced, and the number of the extraction electrodes provided in each layer must be also decreased.
Further, in the multilayer capacitor, from the viewpoint of preventing exfoliation of the terminal electrode due to a thermal shock, the adhesion of the terminal electrode with respect to the multilayer capacitor element assembly must be increased. As this technique, like a technology described in Patent Reference 1, there can be considered a configuration in which a plurality of extraction electrodes are provided to one internal electrode to increase the number of the extraction electrodes and the number of the extraction electrodes joined to each terminal electrode is increased.
In this configuration, however, since the number of the extraction electrodes is increased, realization of a high ESR is obstructed.
Furthermore, the multilayer capacitor disclosed in Patent Reference 1 includes a configuration in which an internal electrode and a dummy electrode having a polarity different from that of the internal electrode are provided in the same layer. Therefore, a short-circuit defect may possibly occur between the internal electrode and the dummy electrode which has a different polarity and is provided in the same layer.
Patent Reference 1: Japanese Patent Application Laid-open No. 2004-40084